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-55°C Electrical Testing from Integra

Posted by Susan Campbell on Wed, Sep 26, 2018 @ 09:32 AM

thermostream1Integra Technologies uses its advanced automated test equipment (ATE) for the purpose of testing at -55°C and beyond. In support of extended temperature testing, we have 35+ ATEs to support the test program development and testing of EEE components. Our successful track record for software development and electrical testing is largely due to:

  • Extensive experience in characterizing  and testing  EEE devices at -55°C and below. This includes Discrete, Passives, Linear, Memory, FPGA, SERDES, Microcontrollers, A/D, D/A, Connectors, Relays, Inductors and Magnetics.
  • Utilizing the largest on-site Test Engineering team, among all test labs worldwide, to develop software and hardware for the extended temperature testing and characterization
  • Integra’s -55°C test strategy includes using one of  our many precision ‘Thermal Temperature Forcing’ units in conjunction with our advanced ATEs. Our  temperature forcing units are testing from -75°C to +200°C.
  • Our custom DUT (Device Under Test)  temperature monitoring process includes
    • Continuous monitoring of temperature at the DUT level for compliance to maintain the target temperature. 
    • Temperature guard-band to account for temperature gradient across the measurement area
    • Calculated temperature ramp rates and soak times to achieve junction temperatureequilibrium using actual packaged devices
    • Precision temperature monitoring thermocouples used to insure highest integrity of test temperature assurance to specification
    • Controlled anti-ESD environment within the Thermal Temperature Forcing units
  • Our cold temperature process has been audited by DLA for compliance
  • High volume cold temperature testing using cold temperature handlers
  • We test both packaged and wafer level cold temperature testing
  • Thousands of lots of historical data running -55°C testing
  • Extensive work with cold temperature storage or cold temperature life test followed by cold temperature electrical testing

 Interested in Learning More? Contact Integra Today!

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Your Single Source Turnkey Solution, from Wafer Processing to Final Test with our Locations Throughout the U.S.!

Open House TODAY!

Posted by Susan Campbell on Tue, Jun 19, 2018 @ 12:09 PM

Stop by and say 'hello' to the Integra group - facility tour, food and drinks! 3:00-7:00 p.m.!

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OPEN HOUSE - June 19th!

Posted by Susan Campbell on Wed, Jun 06, 2018 @ 08:41 AM

Join us for an Open House at our Milpitas, CA facility Tuesday, June 19th! The Open House includes facility tours, wine tasting and hors d'oeuvres. View first hand Integra's ability to take your project from start to finish with their wafer processing and testing equipment all under one roof!

RSVP today! info.sv@integra-tech.com

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Case Study: GaN Wafer Dicing

Posted by Jonny Corrao on Wed, May 30, 2018 @ 02:34 PM

CHALLENGE:
To develop a singulation process for GaN wafers that consistently provides high quality and yields.

CASE STUDY:
GaN-scribe-breakIntegra evaluated the quality of die singulation of mechanical dicing versus scribe and break. A 120µm thick 4" GaN wafer was used for the evaluation.

SOLUTION:

  • Mechanical dicing exhibited superior topside and backside quality compared to scribe and break.
  • The mechanical dicing cut was very clean on the topside of the die with none of the chipping issues that one might normally expect from a hard III-V material.
  • Backside quality from mechanical dicing was acceptable per Mil-Std specifications.
  • Scribe and break demonstrated inferior topside quality compared to mechanical dicing due to the inability to maintain consistent and sufficient force during scribing of the GaN material.
  • Backside quality was also substandard compared to mechanical dicing due to the excessive force required to break and separate the hard III-V material. 

RESULT:
As a result of this evaluation, Integra was able to develop and qualify a high-quality production process for singulating GaN wafers using mechanical dicing.

Interested in finding out more or have your own challenge for Integra to solve?

Let us know!

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GSA Silicon Summit

Posted by Susan Campbell on Wed, Apr 18, 2018 @ 08:04 AM

gsa-summit-logoVisit Integra this Thursday at the GSA Silicon Summit! Stop by Booth 10 and tell Joe, Ron and Jeff hello!

Thursday, April 19th, 2018
8:00 a.m. to 5:00 p.m.
 
San Jose Convention Center
150 West San Carlos Street
San Jose, CA 95113 

Visit Integra Technologies at DMSMS 2017, Booth #920

Posted by Susan Campbell on Mon, Nov 20, 2017 @ 09:12 PM

Integra Technologies provides a complete portfolio of turn-key services to support Military/Space/Aerospace companies threatened with diminishing sources of supply for semiconductor and related EEE parts.  Whether it's Obsolescence Management, Cu Wire Bond Evaluation, PEM Quals, Die Preparation Services, Packaging, Die Extraction and Repackaging (DER), System in Package (SIP), Multi-Chip Modules,  Upscreening, Complex Device Testing, Destructive Physical Analysis (DPA), or Failure Analysis (FA), Integra has an industry leading solution.

PRESENTATION:

Joe Holt from Integra Technologies will be presenting:"Comprehensive Electrical Testing of Suspect Counterfeit Field Programmable Gate Arrays (FPGAs) Proven to Eliminate Counterfeit Devices not Caught by Conventional Mechanical Screening Protocols" during the "Counterfeit Field Forensics and Advanced Detection" training session on Monday, Dec. 4 from 10:30 to noon at the Tampa Convention Center / Rooms 11-17

Please stop by booth #920 and discuss your specific testing requirements with our team of experts.

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New Signs are up!

Posted by Susan Campbell on Mon, Nov 06, 2017 @ 11:19 AM

The new signs are in place at Integra Technologies! Stop by and take a look. Thank you Cordero Printing.

corwil-integra   corwil-integra

 

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Halloween Spirit!

Posted by Susan Campbell on Tue, Oct 31, 2017 @ 04:49 PM

Enjoying Halloween at Integra today!

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Going Green

Posted by Susan Campbell on Wed, Oct 18, 2017 @ 08:15 AM
corwil-going-greenIntegra Technologies Silicon Valley (formerly CORWIL Technology) has partnered with Mynt Systems to take part in helping the environment by going ‘green’. Mynt Systems provided Integra with development, design, engineering and delivery of a turn-key energy efficiency and water conservation project that included efficiency upgrades to the lighting, HVAC, water process, CDA and N2 systems. The combined performance of the holistic energy and water savings project will produce a payback of 4.6 years.

“It has been our pleasure to utilize our deep understanding of energy efficiency technologies and closely held relationships with manufacturers and implementers to create a one of a kind, high yield, investment grade project for Integra and the property ownership,” said Derek Hansen of Mynt Systems. “Mynt Systems has successfully met the performance threshold set for by Integra and was excited to present a unique and groundbreaking project that benefits the all-important triple bottom line of people, planet and profit.”

“Mynt has provided us with the ability to preserve our natural resources while positively impacting bottom lines with short- and long-term cost-saving benefits,” said Matt Bergeron, GM and Vice President at Integra Silicon Valley.  Bergeron went on to say, “Mynt is projecting a 98% reuse of all the process water used in the facility. Conserving this valuable California resource along with the cost savings for Integra is a win/win situation.”

Over 1 Million CSPs Assembled

Posted by Susan Campbell on Tue, Oct 10, 2017 @ 07:30 AM

csp-corwilMILPITAS, CA, October 10, 2017 – Integra Technologies (formerly CORWIL Technology) announced today that it has successfully produced over 1 million CSP’s in its Milpitas Factory.  According to IPC’s standard J-STD-012, implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1mm.

fico1.jpgIntegra produces CSPs using its FICO vacuum assisted mold tool and uses saw singulation to extract the packages from its 70mm x 200mm panel.  “We’ve seen awide variety of product coming through the facility,” says Chip Greely Integra’s VP of Sales and Engineering, “We’ve been happy to see customers using our Assembly Guidelines (see Integra’s website for these guidlines) to make the CSP’s more manufacturable and cost effective.” 

Integra’s CSP process also includes die prep for any size wafer in production, wafer test/sort, Reliability and Package Test. “We are currently testing thousands of CSPs per quarter for one customer,” says Joe Foerstel, Integra’s VP of Test, “We are also performing device level qualification on CSP and bare die to assist our customers in ensuring product life.”

 

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