Earlier this month, CORWIL's own Jonny Corrao, Engineering Manager, presented 'Die-Prep Considerations for IC Device Applications,' at the October MEPTEC Luncheon at the Biltmore Hotel in Santa Clara, CA.
Thank you for coming for all of those who attended. If you weren't able to make the luncheon please download the presentation below.
- Final thickness, surface finish, edge & backside quality, application demands… one wafer, yet endless combinations of process options when working to achieve the highest quality dice possible, prior to IC assembly. This presentation explores various device applications, with consideration to technology node, wafer size, wafer material(s), interconnect, reliability criteria, packing method, and assembly requirements, in concert with die-prep disciplines spanning wafer thinning, singulation, die-sort (pick & place or “plating”), and inspection methods.
Please contact CORWIL with any question you have regarding the presentation or any of CORWIL's services - firstname.lastname@example.org