Low-/Ultra Low-k is an advanced fabrication technology for leading-edge semiconductor devices, utilized to achieve higher performance and smaller feature sizes. The Low-k/Ultra Low-k dielectric material is notorious for its low adhesion strength on silicon and weak bulk mechanical and fracture strength properties, imposing challenges to wafer manufacturing integration.
Delamination, or peeling, is a common defect mode induced during conventional mechanical dicing of any wafer with Low-k technology of 65nm or below. As a result, a laser grooving step is typically introduced to create a shallow trench through the Low-k dielectric layer prior to a mechanical saw cutting through the remaining silicon material. While laser grooving helps to minimize yield loss due to peeling, laser grooving is an additional step that can add cost and lead time to overall assembly process.
In order to address this void in the supply chain, Integra Technologies has invested in laser grooving and has developed a mechanical dicing solution for sawing Low-k/UltraLow-k wafers. Utilizing Integra's proprietary Low-k mechanical saw process, Integra is successful in dicing Ultra-Low k wafers down to 14nm technology while maintaining a dicing yield of greater than 95%.
By developing a Low-k/Ultra Low-k mechanical dicing solution as well as having a Laser Grooving systems, Integra Technologies provides a viable, domestic alternative providing quality and price.
