Webinar: Die Prep Processes and Overview

Posted by Susan Campbell on Tue, Nov 17, 2020 @ 08:30 AM



die-prepWhile quality, functional parts are the end goal for all semiconductor companies, getting from fab to the assembly line is often an undervalued aspect of the IC supply chain. 

Wafer design and characteristics are critical for not only the final product, but also for optimizing an efficient and cost-effective production stream. Utilizing specific process methods can improve die quality and reduce unexpected downstream hiccups. 

Find out more, Wednesday, December 2, 2020, at 1:00 p.m. PST during our 'Die Prep Processes and Overview' Webinar:



Open House TODAY!

Posted by Susan Campbell on Tue, Jun 19, 2018 @ 12:09 PM

Stop by and say 'hello' to the Integra group - facility tour, food and drinks! 3:00-7:00 p.m.!



OPEN HOUSE - June 19th!

Posted by Susan Campbell on Wed, Jun 06, 2018 @ 08:41 AM

Join us for an Open House at our Milpitas, CA facility Tuesday, June 19th! The Open House includes facility tours, wine tasting and hors d'oeuvres. View first hand Integra's ability to take your project from start to finish with their wafer processing and testing equipment all under one roof!

RSVP today!


Case Study: GaN Wafer Dicing

Posted by Jonny Corrao on Wed, May 30, 2018 @ 02:34 PM

To develop a singulation process for GaN wafers that consistently provides high quality and yields.

GaN-scribe-breakIntegra evaluated the quality of die singulation of mechanical dicing versus scribe and break. A 120µm thick 4" GaN wafer was used for the evaluation.


  • Mechanical dicing exhibited superior topside and backside quality compared to scribe and break.
  • The mechanical dicing cut was very clean on the topside of the die with none of the chipping issues that one might normally expect from a hard III-V material.
  • Backside quality from mechanical dicing was acceptable per Mil-Std specifications.
  • Scribe and break demonstrated inferior topside quality compared to mechanical dicing due to the inability to maintain consistent and sufficient force during scribing of the GaN material.
  • Backside quality was also substandard compared to mechanical dicing due to the excessive force required to break and separate the hard III-V material. 

As a result of this evaluation, Integra was able to develop and qualify a high-quality production process for singulating GaN wafers using mechanical dicing.

Interested in finding out more or have your own challenge for Integra to solve?

Let us know!

Request a quote

Visit Us at ICSCRM This Week in Washington DC!

Posted by Susan Campbell on Mon, Sep 18, 2017 @ 03:41 PM


Attending ICSCRM?

Stop by Booth #318 and say 'HI' to Mustafa and Stephen


Assembly and Test Open House Success

Posted by Susan Campbell on Sun, Mar 01, 2015 @ 10:53 PM


Thank you to all of our customers, colleagues and friends who attended our Open House on Wednesday! Visitors were able to take a tour of our newly combined assembly and test facility. The 'under one roof' location allows CORWIL to efficiently take a customer’s device from the beginning, wafer probe, to wafer prep and package assembly, perform package final test, then scan/bake/tape & reel, and into FGI or direct ship to the final end destination.  

If you were not able to stop by, please give your sales rep a call and schedule a tour. You can also take a look at what CORWIL Technology can offer by checking out our video.

CORWIL Technology Combines Assembly and Test in One Location

Posted by Susan Campbell on Wed, Dec 17, 2014 @ 07:21 PM

Milpitas, CA, December 18, 2014 - CORWIL Technology now offers assembly and test services to their customers all under one roof. CORWIL announces the completion of the CORWIL Test Division (CTD) move from their Santa Clara location to the newly remodeled CORWIL facility located at 1635 McCarthy Boulevard, Milpitas, CA. The building redesign includes the addition of 21,500 sq ft to house the CTD equipment which includes ATE such as Teradyne UltraFlex and Advantest 93K, Seiko Epson Handlers, Accretech & TEL Wafer Probers, Burn-in testing equipment and End-of-Line equipment such as scan, laser mark, tape and reel.

The newly remolded building allows customers full access to the CORWIL engineering team at one location and helps to minimize overhead and logistics allowing CORWIL to offer competitive prices for manufacturing services in Silicon Valley.“The decision to combine the two businesses in one building was an easy one,” says Matt Bergeron, CORWIL CEO. “This move will allow our customers easier access to a full turnkey solution. They can watch their product move from assembly to test, reducing their time to market and easing logistical concerns.”

Joe Foerstel, CORWIL Test Division General Manager, said “Being in one location allows CORWIL to efficiently take a customer’s device from the beginning at wafer probe, move on to wafer prep and package assembly, perform package final test, then scan/bake/tape & reel, and into FGI or direct ship to the final end destination.  The new facility also allows CORWIL to offer more on the package/device reliability arena with the ability to perform MLS moisture pre-conditioning and then reflow all onsite, to enhance the current offerings of HTOL, LTOL, THB, HAST, and Temp. Cycling.  CORWIL can do it all, or only what the customer requires from wafer probe to shipping the final tested package.”

 CORWIL Technology


About CORWIL Technology Corporation

CORWIL Technology provides high quality and responsive semiconductor assembly and test services focusing on Hi-Rel, fast-turn and wafer processing markets. Founded in 1990 and based in Milpitas, CA, CORWIL is the premier U.S. provider of full back-end assembly services and is a key partner with leading medical, Mil/Aero and commercial semiconductor companies. For more information about CORWIL, please visit


Die-Prep Considerations for IC Device Applications

Posted by Susan Campbell on Wed, Oct 29, 2014 @ 07:16 AM

MEPTECEarlier this month, CORWIL's own Jonny Corrao, Engineering Manager, presented 'Die-Prep Considerations for IC Device Applications,' at the October MEPTEC Luncheon at the Biltmore Hotel in Santa Clara, CA.

Thank you for coming for all of those who attended. If you weren't able to make the luncheon please download the presentation below.

Die-Prep Considerations for IC Device Applications (.pdf)

  • Final thickness, surface finish, edge & backside quality, application demands… one wafer, yet endless combinations of process options when working to achieve the highest quality dice possible, prior to IC assembly. This presentation explores various device applications, with consideration to technology node, wafer size, wafer material(s), interconnect, reliability criteria, packing method, and assembly requirements, in concert with die-prep disciplines spanning wafer thinning, singulation, die-sort (pick & place or “plating”), and inspection methods.

Please contact CORWIL with any question you have regarding the presentation or any of CORWIL's services -