September 2022 FAQ: Electrical Testing
Take a look at some of our most frequently asked questions:
Q: What does DC Testing Cover?
A: Usually only the first few transistors of each pin. Mostly static voltage, current and power. Complex DC testing could involve dynamic voltage, current and power.
Q: What is DC Testing good for?
A: Electrical over stress, Electro-static discharge pin damage, IDD power supply current failures
Q: What does AC Testing do?
A: AC testing will tell you the speed at which things happen in the device like:
- How long does it take to access an address (access time).
- How long does it take for one signal occur after another (prop. delay).
- Maximum operating frequency.
- Signal rise and fall times.
- But AC testing by itself, while better than just DC testing, still only tests a small percentage of the die at any one time.
Q: What is Functional Testing?
A: Functional testing is making sure that all of the functions that a device can perform are exercised
Q: What type of Testing takes the longest to execute?
A: Functional Testing -the functional test area of a complex parts accounts for 50% to 90% of the overall test development effort and cost.
Q: How should a comprehensive test plan be executed?
A: A comprehensive test plan should cover all the major areas of the part
- DC Tests
- AC Test
- Functional Tests – Functional tests will cover all the functional blocks of the device and account for a significant part of the cost.
Q: Are there different test development protocols for different kinds or semiconductors?
A: Yes, for example, the approach to develop test programs for Microprocessors, FPGAs and Memory are all different. They require unique sets of patterns to be generated that exercises the various functionality of the device.
Is Heterogeneous Integrated (HI) device testing easy?
Heterogeneous Integrated device testing has its own challenges due to integration of multiple chiplets and technologies on a substrate of a board. The key considerations are:
- Design for Test - Integrated design and development of software and hardware across multiple technologies as a package
- Potential known good die testing / singulated die testing
- Test characterization at individual chiplet level
- Modeling the test protocols for HI package where the final product has
- Die to die integration
- Die to package integration
- Package to package integration
- Yield optimization for the HI devices
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