MAY 2024

Advanced Packaging

adv-pkgAdvanced packaging requires a comprehensive approach that encompasses heterogeneous integration, advanced interconnect technologies, effective thermal management, suitable materials and substrates, 3D integration and stacking, reliability testing, advanced manufacturing processes, and robust design and simulation tools. These components are essential for meeting the increasing demands for performance, miniaturization, power efficiency, and reliability in next-generation semiconductor devices and systems. 

Here are some of our latest questions regarding the processes:

Q:  What trends are Integra seeing in substrates?

  • Large Body Sizes
  • High Speed Signals (112Gbps+)
  • Number of high-speed lanes
  • High Power (500-1000W)
  • High Heat (thermal test chips)
  • Large Die Area
  • Memory/Chiplets
  • SiP is driving the larger packages

Q:  What are the key items to identify prior to starting the design? 

  • Target substrate Fab (material), Assembler and Test House
  • Know the manufacture of substrate materials and have the published mechanical and electrical characteristics of the materials
  • Know the active and passive compounds
  • Manufacturers, the procurement lead times and availability of die
  • Know the IP vendors and clarity requirements as soon as possible in the design process and ensure direct communication with the designer to answer questions quickly

Q:  What cooling fundamentals are critical? 

  • Conduction-essential to removing heat, especially to top lid
  • Convection-continued developments in liquid cooling push upper limits
  • Radiation-typically less important unless package sustains high temperatures; useful in the downstream cooling of the assembly
  • Materials and geometry are keys to solving these
  • Materials determine the amount of stretch/force induced into the package
  • Geometry determines where the lines of force are induced - and cause packaging problems because the lines of force do not act along the same line but along parallel lines

Q:  What are some key considerations to flip chip packaging?

  • Knowing bump composition, bump spacing, bump quantity and substrate requirements are all keys to avoiding problems at flip chip
  • The smaller the bumps the more critical the flatness of the substrate
  • The same is true with quantity of bumps - larger bump count = flatness is more critical
  • Not using soldermask defined pads can be beneficial - potential for better solder joint
  • Pad finish should be SOP or ENIPIG - SOP (or similar application) can be beneficial where large bump count
  • Mark Pin 1 on the die!

Q:  What are some key considerations for SiP (System in Package)?

  • Floor planning, part complexity, die proximity and stacking play major roles.
  • Substrate floor plan has to be taken into consideration for stacking and other packaging techniques.
  • Encapsulation is a key consideration - type will be dictated by complex structures and thermal requirements.
  • Common mistakes include: spacing requirements associated with wire bonding and underfill as well as trying to make the SiP too complex.
  • Another common mistake is taking for granted that a die is available when the vendor only offers a packaged part.
  • We have also seen customers who err too much on the side of caution and put as many decoupling capacitors as possible on a SiP where none are needed.

Have more questions? Let us know: