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Over 1 Million CSPs Assembled

Posted by Susan Campbell on Tue, Oct 10, 2017 @ 07:30 AM

csp-corwilMILPITAS, CA, October 10, 2017 – Integra Technologies (formerly CORWIL Technology) announced today that it has successfully produced over 1 million CSP’s in its Milpitas Factory.  According to IPC’s standard J-STD-012, implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1mm.

fico1.jpgIntegra produces CSPs using its FICO vacuum assisted mold tool and uses saw singulation to extract the packages from its 70mm x 200mm panel.  “We’ve seen awide variety of product coming through the facility,” says Chip Greely Integra’s VP of Sales and Engineering, “We’ve been happy to see customers using our Assembly Guidelines (see Integra’s website for these guidlines) to make the CSP’s more manufacturable and cost effective.” 

Integra’s CSP process also includes die prep for any size wafer in production, wafer test/sort, Reliability and Package Test. “We are currently testing thousands of CSPs per quarter for one customer,” says Joe Foerstel, Integra’s VP of Test, “We are also performing device level qualification on CSP and bare die to assist our customers in ensuring product life.”

 

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Assembly and Test Open House Success

Posted by Susan Campbell on Sun, Mar 01, 2015 @ 10:53 PM

corwil-open-house

Thank you to all of our customers, colleagues and friends who attended our Open House on Wednesday! Visitors were able to take a tour of our newly combined assembly and test facility. The 'under one roof' location allows CORWIL to efficiently take a customer’s device from the beginning, wafer probe, to wafer prep and package assembly, perform package final test, then scan/bake/tape & reel, and into FGI or direct ship to the final end destination.  

If you were not able to stop by, please give your sales rep a call and schedule a tour. You can also take a look at what CORWIL Technology can offer by checking out our video.

Die-Prep Considerations for IC Device Applications

Posted by Susan Campbell on Wed, Oct 29, 2014 @ 07:16 AM

MEPTECEarlier this month, CORWIL's own Jonny Corrao, Engineering Manager, presented 'Die-Prep Considerations for IC Device Applications,' at the October MEPTEC Luncheon at the Biltmore Hotel in Santa Clara, CA.

Thank you for coming for all of those who attended. If you weren't able to make the luncheon please download the presentation below.

Die-Prep Considerations for IC Device Applications (.pdf)

  • Final thickness, surface finish, edge & backside quality, application demands… one wafer, yet endless combinations of process options when working to achieve the highest quality dice possible, prior to IC assembly. This presentation explores various device applications, with consideration to technology node, wafer size, wafer material(s), interconnect, reliability criteria, packing method, and assembly requirements, in concert with die-prep disciplines spanning wafer thinning, singulation, die-sort (pick & place or “plating”), and inspection methods.

Please contact CORWIL with any question you have regarding the presentation or any of CORWIL's services - info@corwil.com