“We are excited to implement our new SEC bonder,,” stated Oscar Galimba, Senior Process Engineer. “The new system is very flexible and excellent for prototype and small production runs with die sizes up to 50mm square and a placement accuracy of 0.50um.”
Integra Silicon Valley has seen a large number of new flip chip programs over the past year with many more coming. Learn more about Integra’s flip chip assembly and test and qualification capabilities from their recent tutorials that can be downloaded from our web site.
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