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Case Study: GaN Wafer Dicing

Posted by Jonny Corrao on Wed, May 30, 2018 @ 02:34 PM

CHALLENGE:
To develop a singulation process for GaN wafers that consistently provides high quality and yields.

CASE STUDY:
GaN-scribe-breakIntegra evaluated the quality of die singulation of mechanical dicing versus scribe and break. A 120µm thick 4" GaN wafer was used for the evaluation.

SOLUTION:

  • Mechanical dicing exhibited superior topside and backside quality compared to scribe and break.
  • The mechanical dicing cut was very clean on the topside of the die with none of the chipping issues that one might normally expect from a hard III-V material.
  • Backside quality from mechanical dicing was acceptable per Mil-Std specifications.
  • Scribe and break demonstrated inferior topside quality compared to mechanical dicing due to the inability to maintain consistent and sufficient force during scribing of the GaN material.
  • Backside quality was also substandard compared to mechanical dicing due to the excessive force required to break and separate the hard III-V material. 

RESULT:
As a result of this evaluation, Integra was able to develop and qualify a high-quality production process for singulating GaN wafers using mechanical dicing.

Interested in finding out more or have your own challenge for Integra to solve?

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Assembly and Test Open House Success

Posted by Susan Campbell on Sun, Mar 01, 2015 @ 10:53 PM

corwil-open-house

Thank you to all of our customers, colleagues and friends who attended our Open House on Wednesday! Visitors were able to take a tour of our newly combined assembly and test facility. The 'under one roof' location allows CORWIL to efficiently take a customer’s device from the beginning, wafer probe, to wafer prep and package assembly, perform package final test, then scan/bake/tape & reel, and into FGI or direct ship to the final end destination.  

If you were not able to stop by, please give your sales rep a call and schedule a tour. You can also take a look at what CORWIL Technology can offer by checking out our video.

Die-Prep Considerations for IC Device Applications

Posted by Susan Campbell on Wed, Oct 29, 2014 @ 07:16 AM

MEPTECEarlier this month, CORWIL's own Jonny Corrao, Engineering Manager, presented 'Die-Prep Considerations for IC Device Applications,' at the October MEPTEC Luncheon at the Biltmore Hotel in Santa Clara, CA.

Thank you for coming for all of those who attended. If you weren't able to make the luncheon please download the presentation below.

Die-Prep Considerations for IC Device Applications (.pdf)

  • Final thickness, surface finish, edge & backside quality, application demands… one wafer, yet endless combinations of process options when working to achieve the highest quality dice possible, prior to IC assembly. This presentation explores various device applications, with consideration to technology node, wafer size, wafer material(s), interconnect, reliability criteria, packing method, and assembly requirements, in concert with die-prep disciplines spanning wafer thinning, singulation, die-sort (pick & place or “plating”), and inspection methods.

Please contact CORWIL with any question you have regarding the presentation or any of CORWIL's services - info@corwil.com