Visit Integra Technologies at MEPTEC's 'Heterogeneous Integration' Symposium, this Wednesday, December 5th from 8:00 - 5:00 with exhibits and reception to follow.
ISTFA is going on now at the Phoenix Convention Center. Stop by booth #731 and say Hello!
Integra Technologies uses its advanced automated test equipment (ATE) for the purpose of testing at -55°C and beyond. In support of extended temperature testing, we have 35+ ATEs to support the test program development and testing of EEE components. Our successful track record for software development and electrical testing is largely due to:
- Extensive experience in characterizing and testing EEE devices at -55°C and below. This includes Discrete, Passives, Linear, Memory, FPGA, SERDES, Microcontrollers, A/D, D/A, Connectors, Relays, Inductors and Magnetics.
- Utilizing the largest on-site Test Engineering team, among all test labs worldwide, to develop software and hardware for the extended temperature testing and characterization
- Integra’s -55°C test strategy includes using one of our many precision ‘Thermal Temperature Forcing’ units in conjunction with our advanced ATEs. Our temperature forcing units are testing from -75°C to +200°C.
- Our custom DUT (Device Under Test) temperature monitoring process includes
- Continuous monitoring of temperature at the DUT level for compliance to maintain the target temperature.
- Temperature guard-band to account for temperature gradient across the measurement area
- Calculated temperature ramp rates and soak times to achieve junction temperatureequilibrium using actual packaged devices
- Precision temperature monitoring thermocouples used to insure highest integrity of test temperature assurance to specification
- Controlled anti-ESD environment within the Thermal Temperature Forcing units
- Our cold temperature process has been audited by DLA for compliance
- High volume cold temperature testing using cold temperature handlers
- We test both packaged and wafer level cold temperature testing
- Thousands of lots of historical data running -55°C testing
- Extensive work with cold temperature storage or cold temperature life test followed by cold temperature electrical testing
Interested in Learning More? Contact Integra Today!
Your Single Source Turnkey Solution, from Wafer Processing to Final Test with our Locations Throughout the U.S.!
Stop by and say 'hello' to the Integra group - facility tour, food and drinks! 3:00-7:00 p.m.!
Join us for an Open House at our Milpitas, CA facility Tuesday, June 19th! The Open House includes facility tours, wine tasting and hors d'oeuvres. View first hand Integra's ability to take your project from start to finish with their wafer processing and testing equipment all under one roof!
RSVP today! firstname.lastname@example.org
To develop a singulation process for GaN wafers that consistently provides high quality and yields.
Integra evaluated the quality of die singulation of mechanical dicing versus scribe and break. A 120µm thick 4" GaN wafer was used for the evaluation.
- Mechanical dicing exhibited superior topside and backside quality compared to scribe and break.
- The mechanical dicing cut was very clean on the topside of the die with none of the chipping issues that one might normally expect from a hard III-V material.
- Backside quality from mechanical dicing was acceptable per Mil-Std specifications.
- Scribe and break demonstrated inferior topside quality compared to mechanical dicing due to the inability to maintain consistent and sufficient force during scribing of the GaN material.
- Backside quality was also substandard compared to mechanical dicing due to the excessive force required to break and separate the hard III-V material.
As a result of this evaluation, Integra was able to develop and qualify a high-quality production process for singulating GaN wafers using mechanical dicing.
Interested in finding out more or have your own challenge for Integra to solve?
Let us know!
Thursday, April 19th, 2018
8:00 a.m. to 5:00 p.m.
San Jose Convention Center
150 West San Carlos Street
San Jose, CA 95113
Integra Technologies provides a complete portfolio of turn-key services to support Military/Space/Aerospace companies threatened with diminishing sources of supply for semiconductor and related EEE parts. Whether it's Obsolescence Management, Cu Wire Bond Evaluation, PEM Quals, Die Preparation Services, Packaging, Die Extraction and Repackaging (DER), System in Package (SIP), Multi-Chip Modules, Upscreening, Complex Device Testing, Destructive Physical Analysis (DPA), or Failure Analysis (FA), Integra has an industry leading solution.
Joe Holt from Integra Technologies will be presenting:"Comprehensive Electrical Testing of Suspect Counterfeit Field Programmable Gate Arrays (FPGAs) Proven to Eliminate Counterfeit Devices not Caught by Conventional Mechanical Screening Protocols" during the "Counterfeit Field Forensics and Advanced Detection" training session on Monday, Dec. 4 from 10:30 to noon at the Tampa Convention Center / Rooms 11-17
Please stop by booth #920 and discuss your specific testing requirements with our team of experts.
The new signs are in place at Integra Technologies! Stop by and take a look. Thank you Cordero Printing.